The primary object of the present invention is to provide a monolithic integrated circuit for frequency synthesis using a phase-locked loop without the use of external filter components such as capacitors and resistors.
The following terminology will be used to distinguish between clock signals, the frequencies of clock signals, and the clock period of such clock signals. Clock signals, such as F.sub.X are denoted with a signal name starting with a capital F. The frequency of clock F.sub.X is denoted f.sub.X and the clock period of clock F.sub.X is denoted T.sub.X, which is equal to 1/f.sub.X.
FIG. 1 shows a block diagram of a typical frequency synthesizer 20. The synthesizer 20 consists of a phase detector 22, a loop filter 24, a voltage controlled oscillator (VCO) 26 and two frequency dividers 28 and 30. Components 22 through 28 form a conventional phase-locked loop (PLL) 32. When the synthesizer is in lock, the specified output frequency is EQU f.sub.OUT =N*f.sub.REF =N*f.sub.EXT /M (Eq. 1)
where M and N are the divisors of the frequency dividers 28 and 30, respectively. M and N are typically integers. The reference frequency, f.sub.REF, is generated by dividing an external reference frequency, f.sub.EXT, by M. The specified clock F.sub.REF by means of the phase-locked loop (PLL) 32. The specified output frequency can be adjusted by digitally varying (i.e., programming) the value of N. Therefore, the minimum increment by which f.sub.OUT can be changed, i.e., the resolution of the frequency synthesizer 20, is simply the reference frequency, f.sub.REF.
The phase detector 22 in the synthesizer 20 depicted in FIG. 1 is typically realized using one of several well known circuits. In general, the average (dc) output signal is proportional to the phase difference between the input signals F.sub.REF and F.sub.OUT/N. However, the phase detector 22 typically also produces strong signal components at multiples of the reference frequency. These harmonics must be removed from the input to the VCO 26 by a loop filter 24 to prevent the generation of excessive phase noise at the synthesizer's output.
An example of a prior art phase detector that does not produce signals at multiples of F.sub.REF is shown in FIG. 2. A timing diagram for the circuit in FIG. 2 is shown in FIG. 3. In this phase detector 40, capacitor C.sub.R is used to integrate a current signal I periodically, resulting in a sawtooth voltage waveform across the capacitor. The phase error voltage v(t) is derived by sampling the sawtooth waveform via a sampling switch 42. The sampled voltage is then held on the hold capacitor C.sub.H until the next sample is taken. Unfortunately, the phase detector in FIG. 2 cannot be easily implemented monolithically, especially when the reference frequency is lower than a few kilohertz. For example, if a current signal as low as 10 microamperes could be controlled successfully and the voltage across C.sub.R could swing 5 volts, the required capacitance for C.sub.R in FIG. 2 would be EQU C.sub.R =I*dT/dV=10.sup.-5 *10.sup.-3 /5=2000pF (Eq. 2)
which is too large for monolithic realization. Larger current signals would require an even larger capacitor C.sub.R.
The loop filter 24 in a phase-locked loop is needed both to remove spurious signals that might be generated in the phase detector 22 and to ensure the stability of the feedback loop under circumstances where the loop gain is high. To obtain adequate signal attenuation at f.sub.REF, the loop filter must use an RC circuit having time constants greater than 1/(2*.pi.*f.sub.REF). If the resolution of the synthesizer is high, F.sub.REF can be very low in frequency (e.g., less than 1 kilohertz). As a result, these time constants must be realized using discrete components (i.e., components external to an integrated circuit) because a well controlled resistor of the needed value is generally not available in an integrated circuit. For example, commercially available phase-locked loops require external loop filters.
It is known in the prior art that the response resulting from a long RC time constant can be emulated monolithically with a discrete time system that can be implemented using sampled-data circuit techniques. These techniques have been applied to the design of filters and data acquisition circuits, but have not heretofore been used to implement phase-locked loop systems. The reason for this is that the prior art teaches that the use of a sampled-data circuit in a phase-locked loop would adversely affect loop stability and introduce phase noise. In fact, if any of the conventional prior art phase detectors is used to drive a sampled-data loop filter, the sampling process will mix the higher harmonic components that are present at the phase detector's output down to dc, thereby introducing aliasing distortion in the phase error signal. This distortion can cause excess phase noise at the output and even instability in the feedback system.
The problems described above have precluded the effective implementation of a fully monolithic phase-locked loop. The present invention overcomes these problems by employing a new combination of a sampled-data phase detector and a sampled-data loop filter.